Typical planar inductors of integrated circuits are two-port devices consisting of a number of planar windings wound as a spiral having a rectangular, circular, elliptical or polygonal shape such as disclosed by U.S. Pat. No. 5,416,356.
A widely used figure of merit for (planar) inductors is the quality (Q)-factor, which is the ratio between the amount of magnetic energy stored in the inductor and the power dissipated. Q is related to the inductors impedance as: ##EQU1## wherein: Q=quality factor
Z=complex impedance of the inductor PA1 Im(Z)=imaginary part of Z PA1 Re(Z)=real part of Z. PA1 Ls=self inductance of the inductor PA1 Lm=mutual inductance of the inductor PA1 Rs=Direct Current (DC) resistance of the inductor.
The complex impedance Z is measured across the terminals of the inductor. Neglecting capacitive effects, the Q-factor is roughly determined by: ##EQU2## wherein: L=total inductance of the inductor
The total inductance of the inductor can be divided into a self inductance part, caused by the interaction between the current in a winding and its own generated magnetic field, and a mutual inductance part caused by the interaction between the current in a winding and the magnetic field generated by an adjacent winding or adjacent windings.
Since, as can be seen from (2), Q is inversely proportional to the DC resistance of the inductor, one way to reduce the DC resistance of a planar inductor is to increase the line width of its windings. However, this leads to a decrease of both the mutual and self inductance, whereas it increases the inductor area and the parasitic capacitance associated with the structure. Another measure is to increase the line thickness of the windings. There is, however, an upper limit from a process point of view. In addition, the well known skin effect will make line thicknesses in excess of 4 .mu.m (at frequencies from 2 GHz) not effective.
Increase of the bulk conductivity of the electrically conducting material, i.e. the metal of which the windings are formed, by using gold, silver or copper, will in practical cases not lead to an improvement because, for example, in Gallium Arsenide (GaAs) foundries gold is already used.
U.S. Pat. No. 5,446,311 discloses a manner for reducing the total DC resistance of an inductor by providing spiral planar inductors in different levels of metal, and wherein oppositely positioned windings or turns of the inductors are electrically parallel connected. The reduction in DC resistance depends on the number of parallel connected windings, resulting in an enhancement of the Q factor of the so-formed inductor.
Most of the silicon technologies at present have at least three or more electronically conducting layers of metal for wiring of the circuit. Besides the relatively large surface area occupated by a planar spiral conductor, wherein the region surrounded by the inner most winding is not used for arranging circuit elements, one of the layers or levels of metal has to be used as a cross-under to make a connection of the inner winding of the spiral structure to circuitry of the substrate external to the inductor. Accordingly, only two levels of metal can be used for the inductor windings or turns for the purpose of increasing the Q-factor of a planar inductor.
U.S. Pat. No. 5,559,360 discloses an inductor for semiconductor devices, comprising multiple mutually separated levels of electrically conducting material. Each level comprises a plurality of adjacently arranged strips separated from another. Strips of different levels are electrically series connected which increases the resistance of the individual inductor elements. Those skilled in the art will appreciate that this design does not provide an approach for a high Q inductor.